1. Field
This invention relates, in general, to nonvolatile semiconductor memory devices and, more particularly, to a method and apparatus for controlling the slope of a word line voltage in a nonvolatile semiconductor memory device, a nonvolatile semiconductor memory device including such an apparatus and executing such a method, and a memory system including such a nonvolatile semiconductor memory device.
2. Description
Semiconductor memories are classified into volatile semiconductor memories and non-volatile semiconductor memories. In the volatile semiconductor memories, data are stored and can be read out as long as the power is applied, and are lost when the power is turned off. On the other hand, non-volatile memories such as an MROM (MASK ROM), a PROM (Programmable ROM), an EPROM (Erasable and Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), and flash memories are capable of storing data even with the power turned off.
Of these devices, flash memories are classified into NOR-type flash memories and NAND-type flash memories according to a connection structure of a cell and a bitline. The NOR-type flash memory can be easily adapted to high-speed operation, but has a disadvantage when it comes to providing a high degree of integration. In contrast, the NAND-type flash memory is advantageous when it comes to providing a high degree of integration.
FIGS. 1A and 1B illustrate, respectively an initial state and a programmed state of a flash memory cell transistor having a floating gate.
As shown in FIGS. 1A-B, a single transistor-type flash memory cell 100 generally comprises: a channel formed between a source 105 and a drain 110 on a semiconductor substrate 115; a control gate 120; and a floating gate 130 formed between a dielectric oxide 140 and a gate oxide 150, where dielectric oxide 140, floating gate 130, gate oxide 150, and control gate 120 are stacked on the channel. Floating gate 130 traps electrons, and the trapped electrons are used to establish the threshold voltage of flash memory cell 100. The electrons moving to floating gate 130 are generated by Fowler-Nordheim tunneling (FN), electron injection, etc. Electron injection may be performed by channel hot-electron injection (CHE), channel-initiated secondary electron injection (CISEI), etc. Also, Fowler-Nordheim tunneling (FN) is generally used in flash memory devices for erasing data all at once. Further, when the nonvolatile semiconductor memory device performs a read operation, the data value stored in flash memory cell 100 is determined through sensing the threshold voltage of flash memory cell 100, as discussed in further detail below.
As shown in FIG. 1A, initially flash memory cell 100 is in a “non-programmed” (or “erased”) state and stores a logical “1” therein. In the non-programmed state, flash memory cell 100 has an initial threshold voltage, VTH1, such that when a voltage less than VTH1 is applied to control gate 120, flash memory cell 100 is turned off, but when a voltage greater than VTH1 is applied to control gate 120, flash memory cell 100 is turned on.
Meanwhile, as shown in FIG. 1B, flash memory cell 100 stores a logical “0” when it is in a “programmed” state. In the programmed state, memory cell 100 has a threshold voltage, VTH2 greater than VTH1, such that when a voltage less than VTH2 is applied to control gate 120, flash memory cell 100 is turned off, but when a voltage greater than VTH2 is applied to control gate 120, flash memory cell 100 is turned on.
FIGS. 2A and 2B illustrate, respectively an erase operation and a programming operation for flash memory cell 100.
As seen in FIG. 2A, an erase operation is performed on flash memory cell 100 to store logical a “1”0 therein by applying an erase voltage “VERASE” to the bulk substrate 115 of flash memory cell 100 and grounding control gate 120 to thereby remove electrons from memory cell 100's floating gate 130. Removing electrons from floating gate 130 reduces the threshold voltage of flash memory cell 100 to VTH1, as shown in FIG. 3. FIG. 3 shows that the threshold voltages VTH1 of all of the memory cells in the device will not be the same, but instead the threshold voltages VTH1 will have some distribution and variance about a mean value. In a typical example, threshold voltage VTH1 may be distributed from −1V to −3V. After the erase operation is performed on flash memory cell 100, it is referred to as an “Erased Cell”, and it stores a logical “1.” In general, the erase voltage VERASE is greater than an operating voltage VCC of the NAND flash memory device. For instance, the erase voltage could be 19V while operating voltage VCC is only 5V.
As seen in FIG. 2B, a programming operation is performed on flash memory cell 100 to store a logical “0” therein by applying a program voltage VPGM to control gate 120 of flash memory cell 110, and causing current to flow source 105 and drain 110 to thereby cause electrons in the current to be stored in floating gate 130. Storing electrons in floating gate 130 increases the threshold voltage of flash memory cell 100 to VTH2, as shown in FIG. 3. FIG. 3 shows that the threshold voltages VTH2 of all of the memory cells in the device will not be the same, but instead the threshold voltages VTH2 will have some distribution and variance about a mean value. In a typical example, threshold voltage VTH2 may be distributed from +1V to +3V. After the programming operation is performed on flash memory cell 100, it is referred to as a “Programmed Cell”, and it stores a logical “0.”
A NAND-type flash memory device typically comprises a memory cell array (or memory block) including a plurality of NAND flash memory cell strings (“strings”) 300 connected to bit lines BL0 through BLn-1, respectively. FIG. 4 illustrates a basic NAND flash memory cell string 400. Each string 400 comprises a string selection transistor (SST), a ground selection transistor (GST), and a plurality of flash memory cells 100 serially connected between string selection transistor SST and ground selection transistor GST. Typically, either 16 or 32 flash memory cells 100 are serially connected in flash memory cell string 400. String select transistor SST has a drain connected to a corresponding bit line and a gate connected to a string select line (SSL). Memory cells 100 are connected to corresponding word lines WL0 through WLm-1, respectively. Word lines WL0 through WLm-1, string select line SSL, and ground select line GSL are driven by a row selector circuit (not shown in FIG. 4)
A NAND flash memory device can perform write and program operations on individual flash memory cell strings 400. However, the NAND flash memory device can only perform an erase operation in the unit of one memory block.
In order to program the memory cells of a selected row (or word line) of a NAND flash memory device, the memory cells in a memory block (or a memory cell array) are first erased in order to give each memory cell the threshold voltage VTH1 that is below 0V (all memory cells store a logical “1”). Once the memory cells are erased, program data is loaded onto a page buffer circuit of the NAND flash memory device, and then a high voltage pump circuit generates relatively high voltages for a programming operation. Afterward, the loaded data is programmed into the memory cells of a selected word line by the iteration of program loops. Each of the program loops consists of a bit line setup interval, a program interval, a discharge/recovery interval, and a verification interval.
During the bit line setup interval, bit lines BL0 through BL(n-1) are charged to a power supply voltage VCC or a ground voltage in accordance with the loaded program data. That is, as shown in FIG. 5, a bit line BL for a memory cell to be programmed is charged to the ground voltage, and a bit line BL for a memory cell to be program inhibited (i.e., not programmed) is charged to the power supply voltage VCC. Within the program interval, the program voltage VPGM is supplied to a selected word line and a lower pass voltage VPASS is supplied to the unselected word lines. For memory cells connected to the selected word line and to a bit line charged to the ground voltage, the channel voltage is zero volts, and a bias condition (e.g., 18V) great enough to induce F-N tunneling is satisfied, so electrons are injected from the bulk to the floating gates of the memory cells. On the other hand, as is well known in the art, for memory cells connected to bit lines that are charged to the power supply voltage VCC, the string select transistor (SST) is electrically turned off and the channel voltage of the memory cell connected to the selected word line rises by self-boosting to a voltage level (e.g., 8 volts) sufficient to prevent F-N tunneling and thereby inhibit programming of the memory cell (see FIG. 6). The voltages of the bit lines and the word lines are discharged during the discharge interval, which functions as a recovery interval, and whether the memory cells have been programmed to the desired target threshold voltage is determined during the verification interval.
A step pulse program technique has been developed for programming a flash memory device. FIG. 7 shows a pulse program voltage applied to a selected word line connected to a control gate of a flash memory cell to be programmed. As can be seen in FIG. 7, the program voltage (e.g., 18 V) is applied to the selected word line in a series of program pulses. In between each program pulse is a “verify period” where the data stored in the memory cells being programmed is read. When it is determined that a memory cell connected to the selected word line is programmed as desired, then as shown in FIG. 5, further programming of that memory cell is inhibited for this program operation by charging the associated bit line for the memory cell to VCC.
Typically, in the memory cells of a nonvolatile semiconductor memory device, a programming operation and an erase operation can be performed repeatedly. Flash memory cells are programmed in units of one page. That is, for example, flash memory cells comprising 512 bytes of memory are simultaneously programmed. Meanwhile, flash memory cells are erased in units of one block. That is, for example, flash memory cells comprising 32 pages (e.g., 16 kbytes of memory) are simultaneously programmed.
To read the data stored in a memory cell, a voltage VREAD is applied to the control gate of the memory cell. VREAD is selected to fall between VTH1 and VTH2, i.e., VTH1<VREAD<VTH2. For example, where VTH1 is typically −2V and VTH1 is typically +2V, then VREAD may be 0V (ground). In that case, if the memory cell is turned on when VREAD is applied to its control gate, then the memory cell is determined to be an erased cell, storing a logical “1” therein. On the other hand, if the memory cell remains off when VREAD is applied to its control gate, then the memory cell is determined to be a programmed cell, storing a logical “0” therein.
As shown in FIG. 3 above, in general the various memory cells in a memory device have different values for each of the first and second threshold voltages VTH1 and VTH2, the first and second threshold voltages each being distributed around a mean value with some variance. However, if the variance or distribution of threshold voltages becomes too wide, the difference between the first and second threshold voltages becomes less and less, reducing an operating or noise margin for VREAD to read data from a memory cell.
Accordingly, an incremental step pulse program (ISPP) technique has been developed for programming flash memory cells, to reduce the variation of threshold voltages among the flash memory cells of a flash memory device. As shown in FIG. 8, a series of pulses having gradually increasing voltage levels are applied to the selected word line. Otherwise, the operation is the same as that discussed above with respect to FIG. 7. FIG. 9 shows how the threshold voltage distribution changes after the first pulse, the second pulse having a greater voltage than the first pulse, the third pulse having a greater voltage than the second pulse, etc. By using the ISSP technique, the variation in the threshold voltages among the flash memory cells of a flash memory device is reduced.
However, there is a problem with the flash memory cell programming techniques described above, including the ISSP technique. This problem will be explained with respect to FIGS. 10-11.
FIG. 10 shows a flash memory cell string 1000, illustrating parasitic coupling capacitances that exist between the word lines connected to the various memory cells of the string 1000. Of particular interest is the capacitance 1010 between word line 31 and the adjacent string select line (SSL). As illustrated in FIG. 11, this parasitic coupling capacitance can create a problem when word line 31 is selected during a flash memory cell program operation.
In particular, during a flash memory cell program operation a supply voltage level VCC is applied to SSL, raising the channel voltage for all memory cells of the string 1100 to (VCC−VTH). Then, when word line 31 is selected, the program voltage VPGM of a relatively high voltage level (e.g., 15-18 volts) is applied to word line 31 to program the memory cell 1050 connected thereto, while a lower pass voltage VPASS is applied to each of the remaining, unselected word lines. VPASS has a voltage level such that when the bit line is grounded, the voltage is sufficient to turn on the memory cells connected with these unselected word lines, but insufficient to program these memory cells.
As shown in FIG. 11, due to the capacitance 1010 between word line 31 and the adjacent string select line (SSL), the rising edge of the program voltage VPGM creates a voltage spike on the SSL. This spike may increase the voltage at the control gate of the string select transistor (SST) to be VSSL>(VCC+VTH). Meanwhile, as explained above, if the memory cell 1050 connected to the selected word line 31 is intended not be programmed (program inhibited), then the associated bit line is connected to the supply voltage VCC. In that case, when the voltage on the control gate of the SST becomes VSSL>(VCC+VTH), then the SST may turn on, causing a decrease in the channel voltage for memory cell 1050, as shown in FIG. 11. The decrease in the channel voltage of memory cell 1050, combined with the program voltage VPGM applied to the control gate of memory cell 1050 may present a bias condition which permits F-N tunneling to occur for memory cell 1050, thereby programming memory cell 1050, even though such programming is supposed to be inhibited. In other words, the program inhibit operation may fail. Moreover, due to the coupling capacitances, a similar problem may also occur when another word line (e.g., word line 30) located near the SSL is selected.
One proposed solution to address this problem is shown in FIG. 12. In particular, by decreasing the slope (increasing the rise time) of the program voltage VPGM applied to the selected word line, the voltage spike induced by coupling capacitance onto the SSL may be reduced or eliminated so as to prevent the SST from turning on when it is connected to a bit line charged to VCC (program inhibit) during a programming operation. In turn, this prevents the decrease in the channel voltage for the memory cell connected to the selected word line whose programming is to be inhibited. Accordingly, F-N tunneling is prevented for the memory cell, and the program inhibit function operates properly.
However, when the slope of the program voltage VPGM is decreased (rise time is decreased), then the time required for a programming operation is corresponding increased.
Accordingly, it would be advantageous to provide a nonvolatile memory device that can address one or more of the proceeding concerns. It would also be advantageous to provide a method of programming such a nonvolatile memory device. It would further be advantageous to provide a memory system that incorporates such a nonvolatile memory device. Other and further objects and advantages will appear hereinafter.
The present invention comprises method and apparatus for controlling the slope of a word line voltage in a nonvolatile semiconductor memory device, a nonvolatile semiconductor memory device including such an apparatus and executing such a method, and a memory system including such a nonvolatile semiconductor memory device.
In one aspect of the invention, a nonvolatile memory device comprises: a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines: and a word line voltage generator configured to generate first and second sequences of voltage pulses, and to selectively supply one of the first and second sequences of voltage pulses to a selected one of the word lines to program the nonvolatile memory cells connected to the selected word line, wherein a slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses.
In another aspect of the invention, a nonvolatile memory device comprises a nonvolatile memory cell array including plurality of nonvolatile memory cells connected to a plurality of word lines and a plurality of bit lines, the memory cells of each bit line including a plurality of strings, the array further including a plurality of select lines for selecting the strings, and the word lines including at least a first set of one or more word lines and a second set of one or more word lines; and a word line voltage generator configured to generate first and second sequences of voltage pulses to program the nonvolatile memory cells connected to a selected one of the word lines, to supply the first sequence of voltage pulses to the selected word line when the selected word line belongs to the first set of one or more word lines, and to supply the second sequence of voltage pulses to the selected word line when the selected word line belongs to the second set of one or more word lines, wherein the second set of one or more word lines is closer to one of the select lines than the first set of one or more word lines is, and wherein a slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses.
In a further aspect of the invention, a method of programming a nonvolatile memory device including a nonvolatile memory cell array having a plurality of nonvolatile memory cells connected to a plurality of word lines comprises: applying a first sequence of voltage pulses to a first one of the word lines when programming the nonvolatile memory cells connected to the first word line; and applying a second sequence of voltage pulses to a second one of the word lines when programming the nonvolatile memory cells connected to the second word line, wherein a slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses.
In yet another aspect of the invention, a system comprises: a nonvolatile memory device including a nonvolatile memory cell array having a plurality of nonvolatile memory cells connected to a plurality of word lines, and a word line voltage generator configured to generate first and second sequences of voltage pulses, and to selectively supply one of the first and second sequences of voltage pulses to a selected one of the word lines to program the nonvolatile memory cells connected to the selected word line, wherein a slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses; and a memory controller for supplying an address corresponding to the selected word line for writing data to the nonvolatile memory cells connected to the selected word line.